Imager apparatus, driving method, and camera

ABSTRACT

In an XY address type solid-state imager apparatus comprising a solid-state imager having a plurality of pixels two-dimensionally arranged, and horizontal and vertical scanning circuits to read signals of the pixels, the scanning circuits each have a progressive scanning circuit to progressively read pixel signals by a first scanning control signal, and an interlace scanning circuit to read pixel signals with an interlaced manner by a second scanning control signal different from the first scanning control signal, and arbitrarily carries out combining of progressive reading and interlace reading in one frame in accordance with a combination of the respective scanning control signals, and reads pixel signals.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional application of U.S. patent applicationSer. No. 10/910,779 (the entire contents of which are incorporatedherein by reference), titled “IMAGE APPARATUS, DRIVING METHOD, ANDCAMERA,” filed on Aug. 3, 2004, listing Yuichi GOMI, Taishin YOSHIDA,Seisuke MATSUDA, Yukihiro KURODA and Keiichi MORI as the inventors,which claims the benefit of priority from prior Japanese PatentApplication Nos. 2003-285786, filed Aug. 4, 2003; No. 2003-286775, filedAug. 5, 2003; and No. 2003-206850, filed Aug. 8, 2003. The entirecontents of the U.S. patent application and the three Japanese patentapplications are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state imager apparatus havingan imager in which a plurality of pixel cells are arranged in a matrixform, and a driving method therefor, and further, to a camera using thesolid-state imager apparatus.

2. Description of the Related Art

First, a technique relating to a first aspect of the present inventionwill be described. Conventionally, various techniques with respect to ashift register which can be made to scan in predetermined units from anarbitrary position, and a solid-state imager apparatus using the shiftregister are disclosed. For example, in Jpn. Pat. Appln. KOKAIPublication No. 9-163245, as a solid-state imager apparatus capable ofrealizing interlace scanning, there is disclosed a solid-state imagerapparatus having a shift register configured such that a plurality ofunit stages respectively having a plurality of shift register units areconnected in series. Moreover, in Jpn. Pat. Appln. KOKAI Publication No.6-350933, as a shift register which can start to scan from an arbitraryposition, there is disclosed a shift register in which storage units forstoring outputs of the shift register units are provided to the shiftregister units which are unit stages.

Next, a technique relating to a second aspect of the present inventionwill be described. Conventionally, in the field of electronic camera orthe like, from the standpoints of high-speed reading and low electricpower consumption, only the pixels which are necessary and sufficient atthe time of displaying an image before image being picked-up have beenread out. As this type of technique, for example, in Jpn. Pat. Appln.KOKAI Publication No. 2000-004406, there is disclosed a techniquerelating to an electronic camera with the feature that row groups orcolumn groups among a plurality of photoelectric conversion pixelsarranged in a matrix form are selected by a scanning circuit, and due toa desired row or column being arbitrarily selected from among theselected row groups or column groups by a selection circuit, only thepixels of the desired row or column are precisely interlaced and read.

Next, a technique relating to a third aspect of the present inventionwill be described. Generally, a solid-state imager apparatus has a pixelportion in which a plurality of pixel cells respectively having afunction of converting an incident light into an electrical signal arearranged in a matrix form. A configuration using a CCD (Charge CoupledDevice) and a configuration using a MOS (Metal Oxide Semiconductor) aremainly used. The MOS type solid-state imager apparatus is suitable forrealizing a small-sized image sensor because it is easy to load variouscircuits on a same chip. For example, in Jpn. Pat. Appln. KOKAIPublication No. 2002-354343 or No. 2003-46864, there is disclosed oneexample of a conventional MOS type image sensor.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is providedan XY address type solid-state imager apparatus comprising a solid-stateimager having a plurality of pixels two-dimensionally arranged andhorizontal and vertical scanning circuits to read signals of the pixels,wherein the scanning circuits each have a progressive scanning circuitto progressively read out pixel signals by a first scanning controlsignal and an interlace scanning circuit to read pixel signals with aninterlaced manner by a second scanning control signal different from thefirst scanning control signal, and arbitrarily carries out combining ofprogressive reading and interlace reading in one frame in accordancewith a combination of the respective scanning control signals, and readspixel signals.

Here, the scanning circuits each preferably have a scanning driving unitto start to scan from an arbitrary row or column and a scanning stopunit to stop scanning on an arbitrary row or column, and reads anarbitrary area in one frame.

Further, the scanning circuits each are preferably configured such thatshift register circuits which are unit stages are connected in multiplestages, and each shift register circuit further has a plurality ofinformation transmitting units which transmit information by separateclocks.

Furthermore, the scanning circuits each are preferably configured suchthat shift register circuits which are unit stages are connected inmultiple stages, and each shift register circuit further has a pluralityof information transmitting units which transmit information by separateclocks and a storage unit which stores an output of each shift registercircuit.

Moreover, the information transmitting units preferably include clocktype inverters.

According to a second aspect of the present invention, there is provideda camera comprising: a solid-state imager having a plurality of pixelstwo-dimensionally arranged; horizontal and vertical scanning circuitswhich have a progressive scanning circuit to progressively read pixelsignals by a first scanning control signal, and an interlace scanningcircuit to read pixel signals with an interlaced manner by a secondscanning control signal different from the first scanning controlsignal; a scanning control unit which outputs the first scanning controlsignal and the second scanning control signal; and a mode switching unitwhich switches to a predetermined mode, wherein the camera arbitrarilycarries out combining of progressive reading and interlace reading inone frame in accordance with a combination of the first and secondscanning control signals on the basis of a setting of the mode switchingunit, and reads pixel signals.

Here, the scanning circuits each preferably have a scanning driving unitto start to scan from an arbitrary row or column, and a scanning stopunit to stop scanning on an arbitrary row or column, the scanningcircuits reading an arbitrary area in one frame.

According to a third aspect of the present invention, there is provideda solid-state imager apparatus comprising a solid-state imager havingcolor filters in a predetermined arrangement, the solid-state imagerapparatus having a mode in which all pixels are progressively outputted,and a mode in which interlace reading for pixels is carried out in oneframe and pixel signals of pixels which are at a same color phase amongcolor phase coding regulated by the color filters are averaged withrespect to the pixels and outputted.

According to a fourth aspect of the present invention, there is providedan XY address type solid-state imager apparatus comprising a solid-stateimager in which a plurality of pixels having color filters in which atleast some of those are Bayer-patterned are two-dimensionally arranged,and horizontal and vertical scanning circuits to read the pixels, thesolid-state imager apparatus comprising: a signal averaging switch unitwhich averages pixel signals of pixels which are at a same color phaseamong color phase coding regulated by the color filters; and a mode inwhich all pixels are progressively outputted on the basis of controls ofthe scanning circuits, and a mode in which interlace reading for pixelsis carried out in one frame, and signals which have been averaged by thesignal averaging switch unit with respect to the pixels are outputted.

Here, pixels of a part of the solid-state imager are preferably shadingpixels, and the signal averaging switch unit further averages signals ofpredetermined pixels among signals relating to the shading pixels.Preferably, reading is progressively carried out in one frame withrespect to the shading pixels.

Further, the signal averaging switch unit comprises a shading pixelsignal averaging switch unit and an effective pixel signal averagingswitch unit, and controls whether or not it is possible to average thesignals relating to the shading pixels due to the shading pixel signalaveraging switch unit by a first signal, and controls whether or not itis possible to average the pixel signals of the pixels which are at asame color phase among color phase coding regulated by the color filtersdue to the effective pixel signal averaging switch unit by a secondsignal.

The averaging is preferably carried out only in a horizontal direction,and is not carried out in a vertical direction.

In addition, preferably, switching of the mode in which all pixels areprogressively outputted and the mode in which pixels are averaged andoutputted is carried out by driving and controlling the horizontal andvertical scanning circuits and the signal averaging switch unit.

According to a fifth aspect of the present invention, there is provideda solid-state imager apparatus comprising: a pixel portion in which aplurality of pixel cells respectively having functions of converting anincident light into an electrical signal are arranged in a matrix; a rowunit reset unit which can reset the pixel cells of the pixel portion inunits of rows; and a simultaneous reset unit which can reset all of thepixel cells of the pixel portion simultaneously, wherein the solid-stateimager apparatus executes a reset action in units of rows at the rowunit reset unit and a simultaneous reset action at the simultaneousreset unit while switching those.

Here, preferably, the solid-state imager apparatus further comprises avertical scanning circuit to scan rows to be read of the pixel portion,an electronic shutter scanning circuit to determine a timing of anexposure operation when a light is made to be incident to each pixelcell, and a multiplexer to output one of an output of the verticalscanning circuit and an output of the electronic shutter scanningcircuit to the pixel portion, wherein the simultaneous reset unit isconfigured by a part of the multiplexer.

Further, the multiplexer is configured by: a reading output circuitcomprising a transistor to fetch outputs of the vertical scanningcircuit, a capacitance to accumulate reading row selection signals, anda reading output transistor; an electronic shutter output circuitcomprising a transistor to fetch outputs of the electronic shutterscanning circuit, a capacitance to accumulate electronic shutter rowselection signals, and an electronic shutter output transistor; and asimultaneous reset signal fetching transistor in which a source isconnected to a connection between the transistor to fetch outputs of theelectronic shutter scanning circuit and the capacitance to accumulatethe electronic shutter row selection signals, and which has a gate towhich a simultaneous reset pulse is inputted, and a drain connected to asimultaneous reset power supply, and an output line of the readingoutput circuit and an output line of the electronic shutter outputcircuit are in common.

Furthermore, the transistor configuring the respective pixel cells andthe transistor configuring the multiplexer are preferably configured bythe same conductive type MOS transistor.

Moreover, the multiplexer is preferably configured by: a reading outputcircuit comprising a transistor to fetch outputs of the verticalscanning circuit, a capacitance to accumulate reading row selectionsignals, and a reading output transistor; an electronic shutter outputcircuit comprising a transistor to fetch outputs of the electronicshutter scanning circuit, a capacitance to accumulate electronic shutterrow selection signals, and an electronic shutter output transistor; anda simultaneous reset signal fetching transistor in which a source isconnected to a connection between the transistor to fetch outputs of theelectronic shutter scanning circuit and the capacitance to accumulatethe electronic shutter row selection signals, and which has a gate and adrain to which a simultaneous reset pulse is inputted, and an outputline of the reading output circuit and an output line of the electronicshutter output circuit are in common.

In addition, preferably, in an image acquiring operation by thesimultaneous reset, an exposure starting timing is determined by thesimultaneous reset action, and an exposure terminating timing isdetermined by an operation of closing a mechanical shutter.

According to a sixth aspect of the present invention, there is provideda method for driving a solid-state imager apparatus comprising a pixelportion in which a plurality of pixel cells respectively havingfunctions of converting an incident light into an electrical signal arearranged in a matrix, the method comprising: carrying out a row unitreset action in which the pixel cells of the pixel portion are reset inunits of rows and a simultaneous reset action in which all of the pixelcells of the pixel portion are reset simultaneously while switchingthose.

Additional objects and advantages of the invention will be set forth inthe description which follows, and in part will be obvious from thedescription, or may be learned by practice of the invention. The objectsand advantages of the invention may be realized and obtained by means ofthe instrumentalities and combinations particularly pointed outhereinafter.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate presently preferred embodiments ofthe invention, and together with the general description given above andthe detailed description of the preferred embodiments given below, serveto explain the principles of the invention.

FIG. 1 is a diagram showing a schematic configuration of a solid-stateimager apparatus according to a first embodiment of the presentinvention.

FIG. 2 is a diagram showing a configuration example of shift registers 4and 8 configuring a part of the solid-state imager apparatus shown inFIG. 1 which is further implemented.

FIG. 3 is a timing chart for explanation in detail of a driving method(progressive scanning) for the shift registers 4 and 8 configured as inFIG. 2.

FIG. 4 is a timing chart for explanation in detail of a driving method(interlace scanning) for the shift registers 4 and 8 configured as inFIG. 2.

FIG. 5 is a diagram showing another configuration example of the shiftregisters 4 and 8 configuring a part of the solid-state imager apparatusshown in FIG. 1 which is further implemented.

FIG. 6 is a timing chart for explanation in detail of a driving methodfor the shift registers 4 and 8 configured as in FIG. 5.

FIG. 7 is a diagram showing a schematic configuration of a solid-stateimager apparatus according to a first concrete example of the firstembodiment of the invention.

FIG. 8 is a conceptual illustration of a reading method of thesolid-state imager apparatus according to the first concrete example ofthe first embodiment of the invention.

FIG. 9 is a timing chart showing details in a case where the readingmethod as shown in FIG. 8 in advance is realized by a vertical shiftregister 4 in the first concrete example of the first embodiment of theinvention.

FIG. 10 is a diagram showing a configuration example of the shiftregister that realizes the reading method as shown in FIG. 8 in advancein the first concrete example of the first embodiment of the invention.

FIG. 11 is a diagram showing an example in which a plurality of pixelareas are read by carrying out combination of progressive scanning andinterlace scanning in the horizontal direction and the verticaldirection with respect to the first concrete example of the firstembodiment of the invention.

FIG. 12 is a conceptual illustration of a reading method of asolid-state imager apparatus according to a second concrete example ofthe first embodiment of the invention.

FIG. 13 is a timing chart showing a relationship between vertical shiftregister control signals 5 which are input signals of a vertical shiftregister 4 and output signals with respect to the reading method asshown in FIG. 12 in the second concrete example of the first embodimentof the invention.

FIG. 14 is a timing chart showing a relationship between horizontalshift register control signals 9 which are input signals of a horizontalshift register 8 and output signals with respect to the reading methodas shown in FIG. 12 in the second concrete example of the firstembodiment of the invention.

FIG. 15 is a diagram showing a configuration example of the shiftregister that realizes the reading method as shown in FIG. 12 in thesecond concrete example of the first embodiment of the invention.

FIG. 16 is a diagram showing a configuration of a camera to which thesolid-state imager apparatus according to the first concrete example andsecond concrete example described above is applied as a third concreteexample of the first embodiment of the invention.

FIG. 17 is a conceptual illustration of a solid-state imager apparatusaccording to a second embodiment of the present invention.

FIG. 18 is a block diagram showing a part of the configuration of FIG.17 which is further implemented.

FIG. 19 is a block diagram showing a part of the configuration of FIG.17 which is further implemented.

FIG. 20 is a timing chart (No. 1) showing operations of the solid-stateimager apparatus according to the second embodiment of the invention.

FIG. 21 is a timing chart (No. 2) showing operations of the solid-stateimager apparatus according to the second embodiment of the invention.

FIG. 22 is a block diagram of a camera to which the solid-state imagerapparatus according to the second embodiment of the present invention isapplied.

FIG. 23 is a configuration example of a shift register which can beapplied as a scanning circuit for carrying out progressive scanning andskip scanning in the solid-state imager apparatus according to thesecond embodiment of the invention.

FIG. 24 is a conceptual diagram for explanation of progressive scanningin accordance with the configuration of FIG. 23.

FIG. 25 is a conceptual diagram for explanation of 1/3 skip scanning inaccordance with the configuration of FIG. 23.

FIG. 26 is a diagram showing a configuration of a MOS type solid-stateimager apparatus according to a third embodiment of the presentinvention.

FIG. 27 is a diagram showing a concrete configuration of respectivepixel cells PIX11 to PIX33 shown in FIG. 26.

FIGS. 28A and 28B are diagrams showing concrete configurations of amultiplexer 204 shown in FIG. 26.

FIG. 29 is a timing chart for explanation of reset actions in units ofrows.

FIG. 30 is a timing chart for explanation of another example of resetactions in units of rows.

FIG. 31 is a timing chart for explanation of a driving timing accordingto the third embodiment in which a simultaneous reset is used.

FIG. 32 is a diagram showing a configuration of a MOS type solid-stateimager apparatus according to a modified example of the third embodimentof the invention.

FIGS. 33A and 33B are diagrams showing configurations of the multiplexer204 corresponding to the configuration of FIG. 32.

DETAILED DESCRIPTION OF THE INVENTION First Embodiment

First, an outline of a solid-state imager apparatus comprising a shiftregister which is configured such that a plurality of unit stagesrespectively having a plurality of shift register units are connected inseries and which achieves progressive scanning and interlace scanningwill be described with reference to FIGS. 1 and 2.

A schematic configuration of a solid-state imager apparatus which is tobe the base of a first embodiment of the present invention is shown inFIG. 1, and will be described. As shown in FIG. 1, a pixel matrix 1 isconfigured due to a plurality of pixels 2 being arranged in atwo-dimensional form. A vertical shift register 4 to be driven on thebasis of a vertical shift register control signal 5 is configured by aprogressive scanning shift register unit 4-1 and an interlace scanningshift register unit 4-2. The vertical shift register 4 is connected to avertical selection circuit 3.

On the other hand, a horizontal shift register 8 to be driven on thebasis of a horizontal shift register control signal is configured by aprogressive scanning shift register unit 8-1 and an interlace scanningshift register unit 8-2. The horizontal shift register 8 is connected toa horizontal selection circuit 6. In addition the above description,reference numeral 7 denotes an amplifier for outputting the pixelsignals.

Next, a configuration example of the shift registers 4 and 8 configuringa part of the solid-state imager apparatus shown in FIG. 1 is shown soas to be further implemented in FIG. 2, and will be described.

As shown in FIG. 2, the shift registers 4 and 8 are configured such thata plurality of shift register circuits 24 serving as unit stages areconnected in series. Then, the shift register circuit 24 serving as aunit stage is configured such that information transmitting units 21-1,21-2, and 21-3 for transmitting information respectively by drivingclocks φ1, φ2, and φ3 are connected as shown in the drawing. As theinformation transmitting units 21-1, 21-2, and 21-3, for example, clocktype inverters or the like are used.

In the shift register circuit 24 serving as a unit stage, a first shiftregister unit 22 is configured due to the information transmitting units21-1 and 21-2 being subordinately connected, and a second shift registerunit 23 which is connected so as to have the inputs in common with thefirst shift register unit 22 and to output to the first shift registerunit at one or more following unit stages is configured.

Hereinafter, with reference to the timing charts of FIGS. 3 and 4,driving methods for the shift registers 4 and 8 configured as in FIG. 2will be described in detail.

Note that, in the following description, when an attempt is made todistinguish which unit stage of a shift register circuit eachinformation transmitting unit and shift register unit correspond to,reference numerals in parentheses will be used.

For example, in a case of the first unit stage, it will be described soas to be the shift register circuit 24(1), the information transmittingunits 21-1(1), 21-2(1), and 21-3(1), the first shift register unit22(1), and the second shift register unit 23(1).

First, progressive scanning will be described with reference to thetiming chart of FIG. 3.

In FIG. 3, when an input pulse SR_ST is applied to the first shiftregister circuit 24(1) at a time t₀, at the same time thereof, thesignal is transmitted to the information transmitting unit 21-1(1) bythe information transmitting unit 21-2(1) configuring the first shiftregister unit 22(1) of the first shift register circuit 24(1) when aclock φ2 is at an “H” level.

At the following time t₁, at the same time when the signal istransmitted to the shift register circuit 24(2) at the next unit stageby the information transmitting unit 21-1(1) when a clock φ1 is at the“H” level, an output SR_OUT1 of the shift register circuit 24(1) of thefirst stage is made to be at the “H” level.

Hereinafter, in the same way, signals are successively transmitted intimings when the clock φ2 and the clock φ1 are made to be at the “H”level, and the signals are transmitted to the outputs of the shiftregisters 4 and 8.

In such operations, a clock φ3 is maintained to be at an “L” level, andthe second shift register unit 23 does not operate. The driving methodsfor the shift registers 4 and 8 described above are applied to thesolid-state imager apparatus, whereby pixel signals can be progressivelyread.

Next, interlace scanning will be described with reference to the timingchart of FIG. 4.

In FIG. 4, when an input pulse SR_ST is applied to the first shiftregister circuit 24(1) at the time t₀, at the same time thereof, thesignal is transmitted to the information transmitting unit 21-1(2)configuring the first shift register unit 22(2) of the shift registercircuit 24(2) of the next unit stage by the information transmittingunit 21-3(1) configuring the second shift register unit 23(1) of thefirst shift register circuit 24(1) when the clock φ3 is at the “H”level.

At the following time t₁, at the same time when the signal istransmitted to the shift register circuit 24(3) of the third unit stageby the information transmitting unit 21-1(2) when the clock φ1 is at the“H” level, an output SR_OUT2 of the shift register circuit 24(2) is madeto be at the “H” level.

Then, at a time t₂, when the clock φ3 is at the “H” level, the signal istransmitted to the first shift register unit 22(4) of the shift registercircuit 24(4) of the fourth unit stage by the second shift register unit23(3) at the third stage.

Moreover, at a time t₃, when the clock φ1 is at the “H” level, at thesame time when the signal is transmitted to the shift register circuit24(5) of the fifth unit stage by the information transmitting unit21-1(4), an output SR_OUT4 of the shift register circuit 24(4) is madeto be at the “H” level.

Hereinafter, in the same way, signals are transmitted in timings whenthe clock φ3 and the clock φ1 are made to be at the “H” level, and thesignals are transmitted every other stage to the outputs of the shiftregisters 4 and 8.

In such operations, the clock φ2 is maintained to be at the “L” level,and the information transmitting unit 21-2(1) in the first shiftregister unit 22 does not operate.

The driving methods of the shift registers 4 and 8 described above areapplied to the solid-state imager apparatus, whereby pixel signals canbe read out with an interlaced manner. Note that it is recommended thatintervals at which the pixels are interlaced be changed by changing theoutput address of the second shift register unit 23.

Next, another configuration example of the shift registers 4 and 8configuring a part of the solid-state imager apparatus shown in FIG. 1is further implemented in FIG. 5, and will be described.

As shown in FIG. 5, the shift registers 4 and 8 further comprise astorage unit 32 for storing outputs of a shift register circuit 31 atthe shift register circuit 31 which is a unit stage, and can start toscan from an arbitrary position. In more detail, the shift register isconfigured such that a plurality of shift register circuits 31 which areunit stages are connected in series.

Reference numerals 21-1 and 21-2 are respectively informationtransmitting units for transmitting information by the driving clocks φ1and φ2, and clock type inverters or the like can be used. Referencenumeral 32 is a storage unit for storing the outputs of the shiftregister circuit 31, and has a function of storing information by acontrol signal φm, and of reading information by a control signal φs.

Hereinafter, with reference to the timing chart of FIG. 6, the drivingmethods for the shift registers 4 and 8 configured as in FIG. 5 will bedescribed in detail.

Note that, in the following description, when an attempt is made todistinguish which unit stage of a shift register circuit eachinformation transmitting unit, shift register unit and the likecorrespond to, reference numerals in parentheses will be used.

For example, in a case of the first unit stage, it will be described soas to be the shift register circuit 31(1), the storage unit (1), theinformation transmitting units 21-1(1), 21-2(1), and 21-3(1), the firstshift register unit 22(1), and the second shift register unit 23(1).

First, when an input pulse SR_ST is applied to the shift registercircuit 31(1) at the time t₀, at the same time thereof, the signal istransmitted to the information transmitting unit 21-1(1) by theinformation transmitting unit 21-2(1) when the clock φ2 is at the “H”level.

At the time t₁, at the same time when the signal is transmitted to theshift register circuit 31(2) of the next unit stage by the informationtransmitting unit 21-1(1) when the clock φ1 is at the “H” level, theoutput SR_OUT1 of the shift register circuit 31(1) is made to be at the“H” level.

Hereinafter, in the same way, signals are transmitted in timings whenthe clock φ2 and the clock φ1 are made to be at the “H” level, and thesignals are transmitted to the outputs of the shift register.

At the time t₂, when the φm is made to be at the “H” level, the outputsignal SR_OUT4 of the shift register circuit 31(4) is stored in thestorage unit 32(4).

Next, at the time t₃, when the φs is made to be at the “H” level, themaintained information is read out of the storage unit 32(4), and thesignals are transmitted to the information transmitting unit 21-1(4).

Subsequently, at a following time t₄, when the clock φ1 is at the “H”level, at the same time when the signal is transmitted to the shiftregister circuit 31(5) of the fifth unit stage by the informationtransmitting unit 21-1(4), the output SR_OUT 4 of the shift registercircuit is made to be at the “H” level.

Hereinafter, the shift registering operation is repeated in the timingswhen the clock φ2 and the clock φ1 are made to be at the “H” level. Notethat, in FIGS. 5 and 6, the configuration and the timing for stoppingthe shift registering operation are not specified. However, the shiftregistering can be stopped at an arbitrary position by using a shiftregister with the so-called reset function which has been well known.

Accordingly, the shift registers 4 and 8 shown in FIG. 5 are applied tothe solid-state imager apparatus as shown in FIG. 1, whereby anarbitrary pixel area can be read.

However, in the best mode of the present invention, by using theabove-described technique as the base, reading of an area is carried outwhile interlace the pixels by operating the vertical shift registercontrol signals 5 and the horizontal shift register control signals 9,whereby a frame rate can be switched while maintaining to fix a readingregion, and moreover, it is possible to read the area at a high-speed.

Namely, the solid-state imager apparatus according to the best mode ofthe present invention is an XY address type solid-state imager apparatuswhich comprises the pixel matrix 1 having the plurality of pixels 2two-dimensionally arranged, and the horizontal shift registers 8 and thevertical shift registers 4 for reading the signals of the pixels 2. Thesolid-state imager apparatus has the feature that the respectiveregister 4 and 8 have progressive scanning shift register units 4-1 and8-1 for progressively reading pixel signals and interlace scanning shiftregister units 4-2 and 8-2 for reading pixel signals with an interlacedmanner, and the combination of progressive scanning and interlacescanning is arbitrarily carried out by a combination of these shiftregister units, and the pixel signals are read out. Moreover, therespective shift registers 4 and 8 are characterized by starting to scanfrom an arbitrary row or column, or stopping scanning on an arbitraryrow or column, and reading an arbitrary area in one frame.

The respective shift registers 4 and 8 are configured such that theshift register circuits 24 which are unit stages are connected so as tobe in plural stages, and each shift register circuit 24 further has aplurality of information transmitting units 21-1, 21-2, and 21-3 fortransmitting information by different clocks. Or, the respective shiftregisters 4 and 8 are configured such that the shift register circuits31 which are unit stages are connected so as to be in plural stages, andeach shift register circuit 31 further has a plurality of informationtransmitting units 21-1 and 21-2 for transmitting information bydifferent clocks, and the storage unit 32 for storing the outputs of therespective shift register circuits 31. The information transmittingunits 21-1, 21-2, and 21-3 may be configured of clock type inverters orthe like.

Further, as a camera, the camera has the pixel matrix 1 having theplurality of pixels 2 two-dimensionally arranged, the horizontal andvertical shift registers 4 and 8 which have the progressive scanningshift register units 4-1 and 8-1 for progressively reading pixel signalsand the interlace scanning shift register units 4-2 and 8-2 for readingpixel signals with an interlaced manner by the vertical shift registercontrol signals 5 and the horizontal shift register control signals 9, ascanning control unit for outputting the vertical shift register controlsignals 5 and the horizontal shift register control signal 9, and a modeswitching unit for switching to a predetermined mode. The camera has thefeature that a combination of progressive scanning and interlacescanning is arbitrarily carried out in one frame by a combination of theabove-described scanning control signals, and the pixel signals are readout. The respective shift registers 4 and 8 have a configuration inwhich scanning is started from an arbitrary row or column, and thescanning is stopped on an arbitrary row or column, and can read anarbitrary area in one frame.

Hereinafter, some concrete examples according to the first embodiment ofthe invention will be described. In FIG. 7, a schematic configuration ofthe solid-state imager apparatus according to a first concrete exampleof the present invention is shown. As shown in FIG. 7, the pixel matrix1 is configured such that the plurality of pixels 2 aretwo-dimensionally arranged. The horizontal shift registers 4 to bedriven on the basis of the vertical shift register control signals 5 isconfigured of the progressive scanning shift register unit 4-1 forprogressively carrying out shift registering operations, the interlacescanning shift register unit 4-2 for carrying out shift registeringoperations with predetermined intervals, and a storage unit 4-3 whichstores the outputs of the shift registers and starts the shiftregistering operations from an arbitrary row. Then, the progressivescanning shift register unit 4-1, the interlace scanning shift registerunit 4-2, and the storage unit 4-3 are operated by respectivelyseparated control clocks or control pulses. In FIG. 7, these controlclocks and control pulses are all together shown as the vertical shiftregister control signals 5. The vertical shift register 4 is connectedto the vertical selection circuit 3.

Then, the horizontal shift registers 8 to be driven on the basis of thehorizontal shift register control signals is configured of theprogressive scanning shift register unit 8-1 for progressively carryingout shift registering operations, the interlace scanning shift registerunit 8-2 for carrying out shift registering operations withpredetermined intervals, and a storage unit 8-3 which stores the outputsof the shift registers and starts the shift registering operations froman arbitrary column. The progressive scanning shift register unit 8-1,the interlace scanning shift register unit 8-2, and the storage unit 8-3are operated by respectively separated control clocks or control pulses.In FIG. 7, these control clocks and control pulses are all togethershown as the horizontal shift register control signals 9. The horizontalshift register 8 is connected to the horizontal selection circuit 6 forselecting the pixel columns of the pixel matrix 1. In addition to theabove description, reference numeral 7 denotes an amplifier outputtingpixel signals.

In such a configuration, the vertical shift register 4 and thehorizontal shift register 8 appropriately control the vertical shiftregister control signals 5 and the horizontal shift registers 9, wherebyprogressive scanning as shown above in FIG. 3 and interlace scanning asshown above in FIG. 4, and further, area selecting scanning as shown inFIG. 6 can be obtained.

Here, a conceptual illustration of a reading method of the solid-stateimager apparatus according to the first concrete example is shown inFIG. 8.

FIG. 8 shows ranges of the pixel matrix in a case where progressivescanning and four pixel interlace scanning are repeatedly carried out inthe vertical direction and progressive scanning is carried out in thehorizontal direction. Then, in FIG. 8, the oblique line portionscorrespond to the ranges of the pixels to be read.

Hereinafter, a relationship between the vertical shift register controlsignals 5 which are input signals and output signals when the readingmethod as shown above in FIG. 8 is achieved by the vertical shiftregister 4 in the first concrete example is shown in the timing chart ofFIG. 9, and will be described in detail. Here, the description willappropriately refer to FIG. 10. The respective configurations of FIG. 10are duplicate with the above-described contents, and therefore, detaileddescriptions thereof will be omitted. In the following description, whenan attempt is made to distinguish which unit stage of a shift registercircuit each information transmitting unit and shift register unitcorrespond to, reference numerals in parentheses will be used. Forexample, in a case of the first unit stage, it will be described so asto be the shift register circuit 40(1), the information transmittingunits 21-1(1), 21-2(1), and 21-3(1), and the storage unit 32(1).

As shown in FIG. 9, at the vertical shift register 4, when a start pulseVSR_ST is applied thereto and shift registering operations are carriedout, output signals are outputted in timings when the clock φv1 is madeto be at the “H” level.

When progressive scanning is carried out, the signals are transmitted tothe next stage by the progressive scanning shift register unit 4-1 intimings when the clock φv2 is made to be at the “H” level. On the otherhand, when interlace scanning is carried out, the signals aretransmitted to the stages which are plural stages later designated bythe interlace scanning shift register unit 4-2 in timings when the clockφv3 is made to be at the “H” level.

First, at the time t₀, when a start pulse VSR_ST is applied, at the sametime thereof, the signal is transmitted to the shift register circuit40(1) of the first stage when the clock φv2 is at the “H” level. Next,at the time t₁, when the clock φv1 is made to be at the “H” level, thesignal is outputted to an output VSR_OUT1 of the shift register circuit40(1).

At the time t₂, when the clock φv2 is made to be at the “H” level, thesignal is transmitted to the shift register circuit 40(2) at the secondstage, and when the clock φv1 is at the “H” level at the time t₃, thesignal is outputted to an output VSR_OUT2 of the shift register circuit40(2).

Next, at the time t₄, when the clock φv3 is made to be at the “H” level,the signal is transmitted to the shift register circuit 40(7) at theseventh stage by an interlace scanning shift registering operation, andwhen the clock φv1 is made to be at the “H” level at a time t₅, thesignal is outputted to an output VSR_OUT7 of the shift register circuit40(7). Hereinafter, the cycle of the times t₁ to t₅ is repeated, and dueto progressive scanning and four pixel interlace scanning beingrepeated, the reading method shown in FIG. 8 is achieved.

As described above, in the first concrete example, the method forreading a pixel matrix due to a combination of progressive scanning andfour pixel interlace scanning of the vertical shift register 4 has beenshown. However, repetition of progressive scanning and repetition ofprogressive scanning of interlace scanning can be arbitrarily carriedout by a combination of the timings of the clock φv2 and the clock φv3.Further, as the number of interlace of the interlace scanning, a desiredvalue can be obtained by changing the configuration of the respectiveinterlace scanning shift register units 4-2.

Moreover, reading of the pixel matrix due to a combination ofprogressive scanning and interlace scanning is not limited to only thevertical direction, and can be applied to the reading in the horizontaldirection and to reading due to a combination of the both. For example,a conceptual illustration of FIG. 11 shows an example in which aplurality of pixel areas are read out by carrying out scanning intowhich progressive scanning and interlace scanning are combined in thehorizontal direction and the vertical direction. Namely, in FIG. 11, theoblique line portions correspond to the ranges of the pixels to be read.

In this way, in accordance with the solid-state imager apparatusaccording to the first concrete example, by operating the vertical shiftregister control signals 5 and the horizontal shift register controlsignals 9, a method for reading pixels can be switched in accordancewith a purpose without the circuit configuration being changed.

Because a schematic configuration of a solid-state imager apparatusaccording to a second concrete example of the present invention is incommon with that shown above in the first concrete example (FIG. 7),here, configurations which are the same as those of FIG. 7 are referredwith the same reference numerals.

FIG. 12 is a conceptual illustration of a reading method of thesolid-state imager apparatus according to the second concrete example ofthe present invention. Namely, in FIG. 12, ranges of scanning the pixelmatrix in a case where, two-pixel interlace scanning is carried out ontoonly a certain area in the horizontal direction, and two-pixel interlacescanning is carried out only onto only a certain area in the verticaldirection are shown. Then, the oblique line portions in FIG. 12 show thepixels to be read out.

Note that the shift registers 4 and 8 of the solid-state imagerapparatus according to the second concrete example are as those shown bythe configuration of FIG. 15. Then, the vertical shift register 4 andthe horizontal shift register 8 appropriately control the vertical shiftregister control signals 5 and the horizontal shift register controlsignals 9, whereby progressive scanning as shown above in FIG. 3 andinterlace scanning as shown above in FIG. 4, and further, area selectingscanning as shown in FIG. 6 can be obtained.

Hereinafter, the reading method shown in FIG. 11 in accordance with thesolid-state imager apparatus according to the second concrete example ofthe present invention will be described in more detail with reference totiming charts of FIGS. 13 and 14.

First, a relationship between the vertical shift register controlsignals 5 which are input signals and output signals of the verticalshift register 4 is shown with regard to the reading method as shownabove in FIG. 12 in the second concrete example of the present inventionis shown in the timing chart of FIG. 13, and will be described indetail.

Here, the description will appropriately refer to FIG. 15. Because therespective configurations of FIG. 15 are duplicate with theabove-described contents, and detailed descriptions thereof will beomitted. In the following description, when an attempt is made todistinguish which unit stage of a shift register circuit eachinformation transmitting unit and shift register unit correspond to,reference numerals in parentheses will be used. For example, in a caseof the first unit stage, it will be described so as to be the shiftregister circuit 40(1), the information transmitting units 21-1(1),21-2(1), and 21-3(1), and the storage unit 32(1).

In FIG. 13, at the vertical shift register 4, when a start pulse VSR_STis applied and a shift registering operation is being carried out,output signals are outputted in timings when the clock φv1 is made to beat the “H” level. When interlace scanning is carried out, the signalsare transmitted to the stages which are plural stages later designatedby the interlace scanning shift register unit 4-2 in timings when theclock φv3 is made to be at the “H” level. Here, a pulse signal φvm is acontrol pulse for storing the output signals from the vertical shiftregister in the storing unit 4-3 of the vertical shift register 4. A φvsis a control pulse for reading the signals out of the storage unit 4-3of the vertical shift register 4. Further, a φvr is a control pulse forstopping scanning of the vertical shift register.

By the way, at a time tv₀, when the start pulse VSR_ST is applied andthe clock φv3 is made to be at the “H” level, the signal is transmittedto the vertical shift register circuit 40(3) at the third stage.

At a time tv₁, when the clock φv1 is made to be at the “H” level, thesignal is transmitted to an output VSR_OUT3 of the vertical shiftregister circuit 40(3). At a time tv₂, when the clock φv3 is made to beat the “H” level, the signal is transmitted to the vertical shiftregister circuit 40(6) at the sixth stage. At a time tv₃, when the clockφv1 is made to be at the “H” level, the signal is transmitted to anoutput VSR_OUT6 of the vertical shift register circuit 40(6), andtwo-pixel interlace scanning is repeated.

Next, at a time tv₄, when φvm is made to be at the “H” level, an outputsignal from the VSR_OUT 6 is stored in the storage unit 32(6) of thevertical shift register circuit 40(6) at the sixth stage, and at thesame time, due to the φvr being made to be at the “H” level, thescanning of the vertical shift register is stopped.

Next, at a time tv₅, when the φvs is made to be at the “H” level, thesignal is transmitted to the information transmitting unit 21-1(6) fromthe storage unit 32(6) of the vertical shift register circuit 40(6) atthe sixth stage. Then, at a time tv₆, when the clock φv1 is made to beat the “H” level, the signal is transmitted to the output VSR_OUT6 ofthe vertical shift register circuit 40(6), and at a time tv₇, when theclock φvm is made to be at the “H” level, an output signal from theoutput VSR_OUT6 is stored in the storage unit 32(6) of the verticalshift register circuit 40(6) at the sixth stage again.

Hereinafter, two-pixel interlace scanning is repeated from the sixthstage on. As described above, due to the φvm, the φvs, and the φvr beingappropriately controlled, scanning can be carried out onto only anarbitrary range.

Next, a relationship between the horizontal shift register controlsignals 9 which are input signals of the horizontal shift register 8 andoutput signals with regard to the reading method as shown above in FIG.12 in the second concrete example of the present invention is shown inthe timing chart of FIG. 14, and will be described in more detail.

Here, the description will appropriately refer to FIG. 15. Because therespective configurations of FIG. 15 are duplicate with theabove-described contents, and detailed descriptions thereof will beomitted. In the following description, when an attempt is made todistinguish which unit stage of a shift register circuit eachinformation transmitting unit and shift register unit correspond to,reference numerals in parentheses will be used. For example, in a caseof the first unit stage, it will be described so as to be the shiftregister circuit 40(1), the information transmitting units 21-1(1),21-2(1), and 21-3(1), and the storage unit 32(1).

In FIG. 14, at the horizontal shift register 8, when a start pulseHSR_ST is applied and a shift registering operation is being carriedout, output signals are outputted in timings when a clock φh1 is made tobe at the “H” level. When interlace scanning is carried out, signals aretransmitted to the stages which are plural stages later designated bythe interlace scanning shift register unit 8-2 in timings when a clockφh3 is made to be at the “H” level. Here, a pulse signal φhm is acontrol pulse for storing the output signals from the horizontal shiftregister in the storage unit 8-3 of the horizontal shift register 8. Aφhs is a control pulse for reading the signals out of the storage unit8-3 of the horizontal shift register 8. Further, a φhr is a controlpulse for stopping scanning of the horizontal shift register.

By the way, at a time th₀, at the same time when a start pulse HSR_ST isapplied, the clock φh3 is made to be at the “H” level, and the signal istransmitted to the horizontal shift register circuit 40(3) at the thirdstage. Next, at a time th₁, when the clock φh1 is made to be at the “H”level, the signal is outputted to an output HSR_OUT3 of the horizontalshift register circuit 40(3).

Then, at a time th₂, when the clock φh3 is made to be at the “H” level,the signal is transmitted to the horizontal shift register circuit 40(6)at the sixth stage.

Moreover, at a time th₃, when the clock φh1 is made to be at the “H”level, the signal is transmitted to an output HSR_OUT6 of the horizontalshift register circuit 40(6), and two-pixel interlace scanning isrepeated.

Then, at a time th₄, when the φhm is made to be at the “H” level, anoutput signal from the HSR_OUT6 is stored in the storage unit 32(6) ofthe horizontal shift register circuit 40(6) at the sixth stage, and atthe same time, the φhr is made to be at “H” level, and therefore, thescanning of the horizontal shift register is stopped.

Next, at a time th₅, when the φhs is made to be at the “H” level, thesignal is transmitted to the information transmitting unit 21-1(6) fromthe storage unit 32(6) of the horizontal shift register circuit 40(6) atthe sixth stage. Then, at a time th₆, when the clock φh1 is made to beat the “H” level, the signal is transmitted to the output HSR_OUT6 ofthe horizontal shift register circuit 40(6).

Then, at a time th₇, when the clock φhm is made to be at the “H” level,an output signal from the output HSR_OUT6 is stored in the storage unit32(6) of the horizontal shift register circuit 40(6) at the sixth stageagain. Hereinafter, two-pixel interlace scanning is repeated from thesixth stage on.

In the second concrete example, as described above, due to the φhm, theφhs, and the φhr being appropriately controlled, horizontal scanning canbe carried out onto only an arbitrary range. Moreover, in the secondconcrete example, as described above, interlace reading can be carriedout so as to select only an arbitrary area due to a combination of thevertical shift register control signals 9 and the horizontal shiftregister control signals 5.

In the second concrete example of the present invention described above,the method in which only some areas of the pixel matrix are read whilehorizontal and vertical two-pixel interlace scannings are being carriedout has been shown. However, it goes without saying that the interlacescanning may be carried out only in the horizontal direction or thevertical direction. Further, as the number of interlace of the interlacescanning, a desired value can be obtained by changing the configurationsof the respective interlace scanning shift register units 4-2 and 8-2.

Moreover, an arbitrary area is selected by a combination of thehorizontal shift register control signals 5 and the vertical shiftregister control signals 9, and the area may be read out by combiningprogressive scanning and interlace scanning.

In this way, in the solid-state imager apparatus according to the secondconcrete example of the present invention, because reading of an area iscarried out while interlace the pixels by operating the vertical shiftregister control signals 5 and the horizontal shift register controlsignals 9, a frame rate can be switched while maintaining to fix areading region, and it is possible to read the area at a high-speed.

Next, as a third concrete example of the present invention, a camera towhich the solid-state imager apparatus according to the first and secondconcrete examples described above is applied will be described in detailwith reference to the conceptual illustration of FIG. 16.

As shown in FIG. 16, a solid-state imager apparatus 51 is disposed on anoptical path of an object light which is incident via an imaging lens50. Then, the output of the solid-state imager apparatus 51 is connectedto an input of a direct current restoring unit (CDS) 54, and moreover,an output of the direct current restoring unit 54 is connected to inputsof a contrast AF detecting unit 55 and an image processing unit 56 via aswitch unit 60.

A zoom lens conceptually included in the imaging lens 50 is controlledto drive on the basis of a detected result of the contrast AF detectingunit 55. An output of the image processing unit 56 is connected toinputs of a display unit 57 such as an LCD and a medium recording unit58. An output of a synchronous timing generating unit 52 for generatingclock signals is connected to the inputs of the direct current restoringunit 54 and a scanning control unit 53. A mode switching unit 59 forsetting various modes as well is connected to the scanning control unit53.

In such a configuration, an object light which is incident via theimaging lens 50 is picked up by the solid-state imager of thesolid-state imager apparatus 51, and pixel signals are outputted. Atthat time, the scanning control unit 53 is controlled on the basis ofvarious modes set by the mode switching unit 59, and vertical shiftregister control signals and horizontal shift register control signalsare outputted to a horizontal shift register and a vertical shiftregister in the solid-state imager apparatus 51 so as to achieve theinterlace scanning, the progressive scanning, the reading of an areadescribed above, and the like. On the basis of the control signals,driving as in the first and second concrete examples described above iscarried out, reading of an area while interlace the pixels is carriedout, and a frame rate is switched while maintaining to fix a readingregion. Moreover, high-speed reading of an area is carried out.

Correlated double sampling is carried out onto the pixel signals in thedirect current restoring unit 54, and by further carrying out A/Dconversion onto the pixel signals, the pixel signals are converted intodigital picture signals, and the digital picture signals are transmittedto the contrast A/F detecting unit 55 or the image processing unit 56 inaccordance with a state of switching by the switch unit 60. At thecontrast A/F detecting unit 55, detection of an object distance based onthe digital picture signals is carried out. On the other hand, at theimage processing unit 56, for example, color signal generatingprocessing, matrix conversion processing, and other various imageprocessings are carried out, and the processed signals are outputted tothe display unit 57 or the medium recording unit 58. On this displayunit 57, various displays are carried out on the basis of the digitalpicture signals. On the other hand, the medium recording unit 58 isconfigured by, for example, a card interface, a memory card, and thelike, and the digital picture signals are recorded in the mediumrecording unit 58.

In this way, in the camera according to the third concrete example ofthe invention, in the solid-state imager apparatus, by carrying outreading-out due to a combination of progressive scanning and interlacescanning, or reading of an area while interlace the pixels, on the basisof the vertical shift register control signals 9 and the horizontalshift register control signals 5, a frame rate can be switched whilemaintaining to fix a reading region. Therefore, it is possible to readthe area at a high-speed, and as a result, reading methods suitable forvarious (AF, display, recording, or the like) modes can be selected.

Namely, the interlace scanning is suitable for a case where continuousdisplay is carried out at a short frame rate on the display unit 57, andreading of an area is suitable for a case where the pixel signals areobtained from the respective portions on the screen and a contrast valueis analyzed, and multiple A/F is carried out. A combination of those issuitable for, for example, a case where display is carried out so as tofollow up a high-speed object, or the like. However, it is easilyrealized in such a manner that the scanning control unit 53 controls theoutput timings of the vertical shift register control signals and thehorizontal shift register control signals on the basis of a setting ofthe above-described mode switching unit 59.

The best modes for implementing the present invention has been describedabove. However, the present invention is not limited to the first tothird concrete examples described above, and it goes without saying thatvarious improvements and modifications are possible within a range whichdoes not deviate from the gist of the present invention.

Second Embodiment

First, a conceptual illustration of a solid-state imager apparatusaccording to a second embodiment of the present invention is shown inFIG. 17, and block diagrams showing the configuration of FIG. 17 whichis further implemented are shown in FIGS. 18 and 19. Hereinafter, thesolid-state imager apparatus according to the second embodiment of thepresent invention will be described in detail with reference to theseFIGS. 17 to 19.

In these FIGS. 17 to 19, a pixel portion 101 serving as a solid-stateimager is configured such that a plurality of pixels aretwo-dimensionally arranged in a matrix form. In more detail, the pixelportion 101 is configured by a shading pixel portion 101 a which outputsa signal corresponding to a black level, and an effective pixel portion101 b which receives an object light and generates an electric charge tooutput a pixel signal. Further, the surface of the respective pixels ofthe shading pixel portion 101 a is covered with, for example, a shadingfilm such as aluminum or the like, and color filters are disposed on thesurfaces of the respective pixels of the effective pixel portion 101 b.Moreover, P(i−4, k−3) to P(i+3, k+4) shown in FIG. 18 denote a pluralityof pixel addresses of the shading pixel portion 101 a which are arrangedin the pixel portion 101, and P(j−8, k−3) to P(j+7, k+4) shown in FIG.19 denote a plurality of pixel addresses of the effective pixel portion101 b which are arranged in the pixel portion 101.

Moreover, “R”, “G”, and “B” shown in FIGS. 18 and 19 respectively denotepixels which are sensitive to a red light among the effective pixels(hereinafter, R pixels), pixels which are sensitive to a green lightamong the effective pixels (hereinafter, G pixels), and pixel which aresensitive to a blue light among the effective pixels (hereinafter, Bpixels). With respect to the R pixels, G pixels, and B pixels, the Gpixels are arranged in a checkered form, and the R pixels and the Bpixels are line-progressively arranged (in a Bayer pattern) at theremaining other portions. “OB” denotes a shading pixel.

A vertical scanning circuit 120 progressively scans vertical signallines by row selection signals, and progressively reads pixel signalsfrom the shading pixel portion 101 a and the effective pixel portion 101b. Then, the vertical scanning circuit 120 is configured by n (n is anatural number) vertical scanning circuit units. Codes 120-(k−3) to120-(k+4) denote vertical scanning circuit units in the vicinity of thekth (k is a natural number) vertical scanning circuit unit among the nvertical scanning circuit units.

A signal transfer switch unit 114 is controlled to drive by a signaltransfer clock CKT. In more detail, signal transfer switches 114-(i−4)to 114-(i+3) and 114 -(j−8) to 114-(j+7) which configure the signaltransfer switch unit 114 transfer the pixel signals in the rows selectedby the vertical scanning circuit 120 to capacitative elements 113-(i−4)to 113-(i+3) and 113-(j−8) to 113-(j+7) at the following stages.

A line memory unit 113 is configured by m (m is a natural number)capacitative elements, and temporarily stores the signals of pixels ofone row. The codes 113-(i−4) to 113-(i+3) and 113-(j−8) to 113-(j+7)shown in FIGS. 18 and 19 denote the capacitative elements in thevicinities of the ith (i is a natural number) and the jth (j is anatural number) capacitative elements among the m capacitative elements.

A signal averaging switch unit 112 is a switch for averaging the signalsstored in the line memory unit 113, and is broadly divided into ashading pixel signal averaging switch unit 112 a for averaging thesignals of the shading pixels stored in the line memory unit 113 and aneffective pixel signal averaging switch unit 112 b for averaging thesignals of the effective pixels stored in the line memory unit 113.

The shading pixel signal averaging switch unit 112 a is arranged everyother column, and when a clock CKAVE1 is made to be at the “H” level, apredetermined number (here three columns) of shading pixel signals areaveraged. For example, when the clock CKAVE1 is made to be at the “H”level, the shading pixel signal averaging switches 112-(i−1) and112-(i+1) are operated so as to electrically connect to the capacitativeelements 113-(i−1), 113-(i+1), and 113-(i+3). Further, for example, theshading pixel signal averaging switches 112-(i−3) and 112-(i+3), or thelike are provided such that the circuit configuration for each column,i.e., the layout is made to be uniform, and are connected so as to notfunction even when the clock CKAVE1 is made to be at the “H” level. Inaccordance with such a connection, it is made to be the same as theconnecting form of the effective pixel signal averaging switch unit 112b.

On the other hand, the effective pixel signal averaging switch unit 112b is configured such that the respective signals of the R pixels, the Gpixels, and the B pixels are averaged in units of a predetermined numberpixels (here, three pixels), and are connected so as to be controlled bya clock CKAVE2.

In this way, in the present embodiment, the pixel signal averagingswitch unit 112 is configured such that, with respect to the signals ofthe shading pixels among the signals stored in the line memory unit 113,averaging of the signals of three pixels is controlled by the clockCKAVE1 by the shading pixel signal averaging switch unit 112 a, and withrespect to the signals of the effective pixels, averaging of the signalsof three pixels of a same color is controlled by the clock CKAVE2 by theeffective pixel signal averaging switch unit 112 b.

A horizontal scanning circuit 110 is for progressively driving thehorizontal selecting switch unit 111, and is configured by m horizontalscanning circuit units. Namely, codes 110-(i−4) to 110-(i+3) and110-(j−8) to 110-(j+7) denote horizontal scanning circuit units in thevicinities of the ith and the jth horizontal scanning circuit unitsamong the m horizontal scanning circuit units.

The horizontal selecting switch unit 111 is controlled by outputs(horizontal selection signals) of the horizontal scanning circuit unit110, and is configured by m horizontal selecting switches. Codes111-(i−4) to 111-(i+3) and 111-(j−8) to 111-(j+7) in FIGS. 18 and 19denote horizontal selecting switches in the vicinities of the ith andthe jth horizontal selecting switches among the m horizontal selectingswitches. Then, in the horizontal selecting switch unit 111, when therespective horizontal selecting switches are made to be in an ON-stateby horizontal selection signals, the pixel signals stored in the linememory unit 113 are transmitted to the horizontal signal lines, andmoreover, the pixel signals are amplified by an output amplifier 130 atthe following stage and are outputted to the exterior.

In the above-described configuration, the present embodiment is asolid-state imager apparatus comprising the pixel portion 101 on whichBayer-patterned color filters are provided. The solid-state imagerapparatus carries out interlace reading for pixels in one frame, andwith respect to the pixels, the solid-state imager apparatus averagesthe pixel signals of the pixels which are at a same color phase amongthe color phase coding regulated by the above-described color filtersare averaged and outputted.

In more detail, an XY address type solid-state imager apparatus isconfigured by the pixel portion 101 in which a plurality of pixelshaving color filters in which at least some of those are Bayer-patternedare two-dimensionally arranged, the horizontal scanning circuit 110 andthe vertical scanning circuit 120 which are for carrying out reading ofthe pixel signals of the pixels. The XY address type solid-state imagerapparatus has the signal averaging switch unit 112 for averaging thepixel signals of the pixels which are at a same color phase among thecolor phase coding regulated by the above-described color filters. Inaddition, the XY address type solid-state imager apparatus carries outinterlace reading for the pixels in one frame on the basis of thecontrols of the above-described scanning circuits 110 and 120, andoutputs signals in which the pixels are averaged by the above-describedsignal averaging switch unit 112.

Moreover, the above-described pixel portion 101 is configured by theshading pixel portion 101 a and the effective pixel portion 101 b, andthe signal averaging switch unit 112 further averages the signals ofpredetermined pixels among the signals relating to the pixels of theshading pixel portion 101 a. At that time, the signals relating to thepixels of the shading pixel portion 101 a are progressively read out inone frame. Then, the signal averaging switch unit 112 comprises theshading pixel signal averaging switch unit 112 a and the effective pixelsignal averaging switch unit 112 b. The signal averaging switch unit 112controls whether or not it is possible to average the signals relatingto the shading pixels due to the shading pixel signal averaging switchunit 112 a by a first signal (CKAVE1), and controls whether or not it ispossible to average the pixel signals of the pixels which are at a samecolor phase among the coding of the color phases regulated by the colorfilters due to the effective pixel signal averaging switch unit 112 b bya second signal (CKAVE2).

Hereinafter, the operations of the solid-state imager apparatusconfigured as described above will be described in more detail withreference to the timing charts of FIGS. 20 and 21. Note that the timingsshown by codes “a” to “p” in FIG. 20 respectively correspond to thetimings shown by the same codes in FIG. 21.

In FIGS. 20 and 21, “VD” is a vertical synchronizing signal, “HD” is ahorizontal synchronizing signal, “CKAVE1” is a clock which controls toturn the shading pixel signal averaging switch unit 112 a ON and OFF,“CKAVE2” is a clock which controls to turn the effective pixel signalaveraging switch unit 112 b ON and OFF, and “CKT” is a clock whichcontrols to turn the signal transfer switch unit 1140N and OFF.

“V-1” to “V-n” are row selection signals, and are the outputs of thevertical scanning circuit units 120-1 to 120-n. “H-1” to “H-m” arehorizontal selection signals for controlling the horizontal selectingswitches 111-1 to 111-m, and are the output signals from the horizontalscanning circuit units 110-1 to 110-m. In addition to the abovedescription, “signal output” is a pixel signal outputted from the outputamplifier 130.

By the way, when the routine proceeds to this operation, the verticalscanning circuit 120 carries out scanning of skipping two rows in thedirection of the arrangement of the vertical scanning circuit units120-1 to 120-n, such as, for example, 120-1, . . . , 120-(k−3), 120-k,120-(k+3), . . . , 120-n, i.e., vertical 1/3 interlace scanning.

Namely, when a row selection signal V-(k−3) outputted from the verticalscanning circuit 120 is made to be at the “H” level within a horizontalblanking period (a period during the time when the horizontalsynchronizing signal HD is being at the “H” level), the pixels P(i, k−3)to P(m, k−3) in the (k−3)th row are selected.

During this period, because the signal transfer clock CKT inputted tothe signal transfer switch unit 114 is at the “H” level, the pixelsignals of the selected pixels P(i, k−3) to P(m, k−3) are stored in thecapacitative elements 113-1 to 113-m. Thereafter, because the clocksCKAVE1 and CKAVE2 inputted to the pixel signal averaging switch unit 112are at the “H” level, the signals of three pixels in every other columnare averaged, and are stored in the line memory unit 113.

Namely, for example, an average of the signals stored in thecapacitative elements 113-(i−4), 113-(I-2), and 113-i is stored as anaverage signal of the shading pixels of three pixels, and for example,an average of the signals stored in the capacitative elements 113-(j−1),113-(j+1), and 113-(j+3) is stored as an average signal of the effectivepixels of three pixels, respectively in the line memory unit 113. Inaccordance with such an operation, averaging of three pixels of ahorizontal same color of the Bayer-patterned R pixels and G pixels iscarried out.

Thereafter, when scanning/selection signals are outputted to thehorizontal scanning circuit units 110-1 to 110-m within a horizontaleffective period (a period during the time when the horizontalsynchronizing signal HD is being at the “H” level), and in a case ofselecting the shading pixel signals, progressive scanning isprogressively carried out such that the horizontal selection signals areoutputted one unit by one unit in a progressive order (H-1, . . . ,H-(i−4), H-(i−3), H-(i−2), H-(i−1), H-i, H-(i+1), H-(i+2), H-(i+3),H-(i+4), . . . ).

On the other hand, in a case of selecting the effective pixel signals,scanning such that the horizontal selection signals are outputted fromone unit of the three units, i.e., 1/3 interlace scanning ( . . . ,H-(j−8), H-(j−5), H-(j−2), H-(j+1), H-(j+4), H-(j+7), . . . ) is carriedout.

When the horizontal scanning is carried out in this way, the three-pixelaverage signals of the shading pixels and the three-pixel averagesignals of the effective pixels which have been stored in the linememory unit 113 are transmitted to the horizontal signal lines via thehorizontal selecting switch unit 111, and are further amplified at theoutput amplifier 130 at the following stage and are converted intosignal outputs.

At this time, the three-pixel average signals of the shading pixels areprogressively outputted, and the three-pixel average signals of theeffective pixels are outputted so as to interlaced the number of thesignals to be 1/3 thereof. In this way, three pixels of the pixelsignals of one row are averaged, and signals of the number of theshading pixels and signals of 1/3 the number of the effective signalsare outputted.

In the next horizontal blanking period, because the vertical scanningcircuit 120 carries out 1/3 interlace scanning, a row selection signalV-k from the vertical scanning circuit 120 is made to be at the “H”level. When the row selection signal V-k is made to be at the “H” levelwithin the horizontal blanking period, the pixels P(l, k) to P(m, k) inthe kth row are selected. During this period, the signal transfer clockCKT inputted to the signal transfer switch unit 114 is at the “H” level,the pixel signals of the selected pixels P(l, k) to P(m, k) are storedin the capacitative elements 113-1 to 113-m of the line memory unit 113.

Thereafter, because the clocks CKAVE1 and CKAVE2 inputted to the signalaveraging switch unit 112 are at the “H” level, the signals of threepixels in every other column are averaged, and the three-pixel averagesignals of the shading pixels and the three-pixel average signals of theeffective signals are respectively stored in the line memory unit 113.

In accordance with the above-described operation, averaging of threepixels of a horizontal same color of the Bayer-patterned G pixels and Bpixels is carried out. Thereafter, when the scanning/selection signalsare outputted to the horizontal scanning circuit units 110-1 to 110-mwithin a horizontal effective period, in a case of selecting the shadingpixel signals, the horizontal scanning is progressively carried out suchthat the horizontal selection signals are outputted one unit by one unitin a progressive order (H-1, . . . , H-(i−4), H-(i−3), H-(i−2), H-(i−1),H-i, H-(i+1), H-(i+2), H-(i+3), H-(i+4), . . . ). In a case of selectingthe effective pixel signals, 1/3 interlace scanning is carried out suchthat the horizontal selection signals are outputted from one unit of thethree units ( . . . , H-(j−8), H-(j−5), H-(j−2), H-(j+1), H-(j+4),H-(j+7), . . . . ).

When the horizontal scanning is carried out in this way, the three-pixelaverage signals of the shading pixels and the three-pixel averagesignals of the effective pixels which have been stored in the linememory unit 113 are transmitted to the horizontal signal lines via thehorizontal selecting switch unit 111, and are further amplified at theoutput amplifier and are converted into signal outputs.

At this time, the three-pixel average signals of the shading pixels areprogressively outputted, and the three-pixel average signals of theeffective pixels are outputted so as to interlaced the number of thesignals to be 1/3 thereof. In this way, three pixels of the pixelsignals of one row are averaged, and the signals of the number of theshading pixels and the signals of 1/3 of the number of the effectivesignals are outputted.

Hereinafter, the pixels in the (k+3)th row to the nth row are selectedevery third row within the vertical blanking period in the same way, andthe pixel signals in each row are outputted within the horizontaleffective period.

In accordance with the above-described reading operation, vertical 1/3interlace reading, horizontal progressively reading of the averagesignals of the three pixels of the shading pixels, and horizontal 1/3interlace reading of the average signals of the three pixels of a samecolor of the effective pixels are carried out. Due to the apparatusbeing operated in this way, because the number of effective pixels to beread are horizontally and vertically compressed into 1/3, it is possibleto read at a high frame rate.

At this time, because the signals of the three pixels of a horizontalsame color are averaged and outputted, a pseudo-color in the horizontaldirection generated by carrying out interlace reading can be suppressed.Further, the circuit scale can be materially reduced as compared withthe case where averaging in the vertical direction is carried out.Moreover, because progressive reading is carried out in a case ofreading the shading pixels, a period during the time of clamping to ashading pixel signal level can be ensured so as to be the same as in thecase of progressive reading.

Next, a camera to which the solid-state imager apparatus according tothe embodiment described above is applied will be described in detailwith reference to a conceptual illustration of FIG. 22.

As shown in FIG. 22, a solid-state imager apparatus 151 is disposed onan optical path of an object light which is incident via an imaging lens150. Then, an output of the solid-state imager apparatus 151 isconnected to an input of a direct current regenerating unit (CDS) 156,and moreover, an output of the direct current regenerating unit 156 isconnected to inputs of a contrast AF detecting unit 157 and an imageprocessing unit 158 via a switch unit.

A zoom lens conceptually included in the imaging lens 150 is controlledto drive on the basis of a detected result of the contrast AF detectingunit 157. An output of the image processing unit 158 is connected to aninput of a display unit 160 such as an LCD, and a medium recording unit161. An output of a synchronous timing generating unit 155 forgenerating a clock signal is connected to the inputs of the directcurrent regenerating unit 156 and a scanning control unit 154. A modeswitching unit 159 for setting various modes as well is connected to thescanning control unit 154.

In such a configuration, an object light which is incident via theimaging lens 150 is picked up by the solid-state imager of thesolid-state imager apparatus 101, and a pixel signal is outputted.

At that time, the scanning control unit 154 is controlled on the basisof the various modes set by the mode switching unit 159, and a verticalshift register control signals and horizontal shift register controlsignals are outputted to a horizontal scanning circuit 153 and avertical scanning circuit 152 in the solid-state imager apparatus 101 soas to achieve the interlace scanning described above, or the like. Onthe basis of this control signal, driving as described above is carriedout, and reading while interlace pixels is carried out.

Correlated double sampling is carried out onto the pixel signal in thedirect current regenerating unit 150, A/D conversion is further carriedout onto the pixel signal, the pixel signal is converted into a digitalpicture signal, and the digital picture signal is transmitted to thecontrast A/F detecting unit 157 or the image processing unit 158 inaccordance with a state of switching by the switch unit. At the contrastA/F detecting unit 157, detection of an object distance based on thedigital picture signal is carried out. On the other hand, at the imageprocessing unit 158, for example, color signal generating processing,matrix conversion processing, and other various image processings arecarried out, and the processed signal is outputted to the display unit160 or the medium recording unit 161. On this display unit 160, variousdisplays are carried out on the basis of the digital picture signal. Onthe other hand, the medium recording unit 161 is configured by, forexample, a card interface, a memory card, and the like, and the digitalpicture signal is recorded thereon in the medium recording unit 161. Inthe camera as an application example, at the solid-state imagerapparatus in the camera, by carrying out reading due to interlacescanning, a frame rate is improved, and it is possible to read an areaat a high-speed, and as a result, reading methods suitable for various(AF, display, recording, or the like) modes can be selected. Namely, theinterlace scanning is suitable for a case where continuous display iscarried out at a short frame rate on the display unit 160.

However, it is easily realized in such a manner that the scanningcontrol unit 154 controls the output timings of the vertical shiftregister control signals and the horizontal shift register controlsignals on the basis of a setting of the above-described mode switchingunit 159.

The embodiment of the present invention has been described above.However, the present invention is not limited thereto, and it goeswithout saying that various improvements and modifications are possiblewithin a range which does not deviate from the gist of the presentinvention.

Namely, for example, the circuit configurations shown in FIGS. 17 to 19are not limited thereto, and it is possible to provide a function ofcanceling FPN of a pixel to the reading circuit, or the like.

Further, in the embodiment, the configuration in which it is possible toaverage horizontal three pixels has been shown. However, it can beconfigured such that it is possible to average horizontal five pixels orto average horizontal seven pixels by changing a repeating period of thesignal averaging switches, and it can be configured such that aplurality of averaging operations can be selectively carried out. Also,in the embodiment described above, it is configured such that signaloutput is carried out on one line. However, it goes without saying thatit can be carried out such that signal output can be carried out onmultiple lines.

Furthermore, in the timing charts of FIGS. 20 and 21, the shading pixelsignals can be read without being averaged due to the CKAVE1 beingmaintained to be at the “L” level, and the effective pixel signals canbe read without being averaged due to the CKAVE2 being maintained to beat the “L” level.

In the above-described embodiment of the invention, the operations ofthe horizontal scanning circuits and the vertical scanning circuits bywhich 1/3 interlace scanning can be carried out has been described.However, in order to carry out such an operation, as an apparatus usinga decoder circuit or an apparatus using a shift register as a scanningcircuit, for example, it can be realized by a method for interlacescanning disclosed in Jpn. Pat. Appln. KOKAI Publication No. 9-163245,and it goes without saying that it is possible to progressively read allthe pixels by carrying out progressive scanning.

Here, a configuration example of a shift register used for a scanningcircuit for carrying out progressive scanning and skip scanning is shownin FIG. 23, and will be described. In FIG. 23, a shift register unit 180of one stage is configured by a first shift register unit 170 comprisingsub units 171 and 172 and a second shift register unit 173. Inputterminals of the first and second shift register units 170 and 173 areconnected in common. Further, the output terminal of the first shiftregister unit 170 is connected to the input terminal of the shiftregister unit at the next stage, and the output terminal of the secondshift register unit 173 is connected to the input terminal of the subunit 172 at a stage which is two stages later. Then, the sub units 171and 172 of the first shift register unit are respectively driven bydriving pulses φ1-1 and φ1-2, and the second shift register unit 173 isdriven by a driving pulse φ2.

In the shift register having such a configuration, provided that drivingsignals are applied to the driving pulses φ1-1 and φ1-2, and the drivingpulse φ2 is made to be in a state in which the second shift registerunit 173 is made to not operate. In this case, when a start pulse φST ofthe shift register is inputted, because the input signal shifts in theshift register as shown by the alternate long and short dash line inFIG. 24, signals are outputted in order of SRout1, SRout2, SRout3, . . ., and progressive scanning can be carried out.

On the other hand, in the shift register, provided that driving signalsare applied to the driving pulses φ1-2 and φ2, and the driving pulseφ1-1 is made to be in a state in which the sub unit 171 is made to notoperate. In this case, when a start pulse φST of the shift register isinputted, because the input signal shifts in the shift register as shownby the alternate long and short dash line in FIG. 25, signals areoutputted in order of SRout3, SRout6, and . . . , and 1/3 interlacescanning can be carried out.

As described above, due to a shift register having a configuration asthat of FIG. 23 being used as a scanning circuit, it is possible toswitch the progressive scanning and the skip scanning. Note that,because switching of the progressive scanning and the skip scanning canbe carried out by controlling the driving pulses, it is possible toswitch the progressive scanning and the interlace scanning on the way ofscanning by changing a driving pulse on the way of scanning, and thescanning in which such that progressive scanning is carried out onto theshading pixel region and interlace scanning is carried out onto theeffective pixel region is possible.

Third Embodiment

First, the outline of a third embodiment of the present invention willbe described. In the third embodiment, at the time of driving thesolid-state imager apparatus having a pixel portion in which a pluralityof pixel cells respectively having a function of converting an incidentlight into electric information are arranged in a matrix form, inaddition to a reset action in units of rows in which the pixel cells ofthe pixel portion are reset in units of rows, a simultaneous resetaction in which all of the pixel cells of the pixel portion aresimultaneously reset in units of rows is used, and these two resetmethods are used while appropriately switching those. In accordancetherewith, a delay at the time of fetching a still image can be reduced.Further, the circuit configuration for carrying out the simultaneousreset action can be achieved by merely adding a simple circuit.

Concretely, for example, in a case of photographing a still image,first, a simultaneous reset action for all the pixel cells is carriedout in a state in which a mechanical shutter is fully open, and theexposure is completed by closing the mechanical shutter. Thereafter,operations of reading signals from the pixel cells are carried out inunits of rows.

Hereinafter, the third embodiment of the present invention will bedescribed in detail with reference to the drawings. FIG. 26 is a diagramshowing a configuration of a MOS type solid-state imager apparatusaccording to the third embodiment of the invention. The solid-stateimager apparatus of the embodiment has a pixel portion 201 configuredsuch that a plurality of pixel cells PIX 211 to PIX 233 are arranged inthe matrix directions (here, only nine pixel cells of the PIX 211 to thePIX 233 are shown in order to simplify the explanation), a verticalscanning circuit 202 used for selecting a row of reading pixels, anelectric shutter scanning circuit 203 used for determining a start ofexposure, a multiplexer 204 for outputting one of the output of thevertical scanning circuit 202 and the output of the electric shutterscanning circuit 203, a noise suppressing circuit 205 for suppressing anoise included in the signal read out in the vertical signal lines V1 toV3, a horizontal scanning circuit 206 for fetching the signals from thenoise suppressing circuit 205 by selectively turning horizontalselecting switches M201 to M203 on and off, an output amplifier 207 foramplifying the fetched signals, and a source of current (load of pixelcells) 209 for generating electric current supplied to the pixel portion201.

Reference numeral 208 denotes a power supply line for the pixel cells(VDDCEL), reference numeral 210 denotes a pulse line for turning thesource of current 209 on and off (LGCEL), reference numeral 211 denotesa reading reset pulse line (RST), reference numeral 212 denotes areading transfer pulse line (TR), reference numeral 213 denotes anelectronic shutter reset pulse line (ERST), reference numeral 214denotes an electronic shutter transfer pulse line (ETR), referencenumeral 215 denotes a pulse line for fetching the outputs of thevertical scanning circuit 202 and the electronic shutter scanningcircuit 203 (VDRRS), reference numeral 216 denotes a simultaneous resetpulse line (ARST), and reference numeral 217 denotes a simultaneousreset power supply (MPXDD). Further, φV1 to φv3 are reading rowselecting lines, φVE1 to φVE3 are electronic shutter row selectinglines, φRST1 to φRST3 are pixel reset pulse lines, φTR1 to φTR3 arepixel transfer pulse lines, V1 to V3 are vertical signal lines, φH1 toφH3 are column selecting lines, and OUT is a sensor output line.

FIG. 27 is a diagram showing a concrete configuration of the respectivepixel cells PIX211 to PIX233 shown in FIG. 26, and is configured of aphotodiode PD1 for converting an incident light into electricinformation, a transfer transistor M1, a reset transistor M2, and apixel amplifier transistor M3. φRST is a pixel reset pulse line, φTR isa pixel transfer pulse line, VDDCEL is a power supply line for pixelcells, PIXOUT is an output line for pixels. Reference numeral 220denotes a floating diffusion (Floating Diffusion, hereinafter called anFD) unit.

FIGS. 28A and 28B are diagrams showing concrete configurations of themultiplexer 204 shown in FIG. 26, and the multiplexer 204 is configuredof a pair of a pixel reset pulse output circuit (FIG. 28A) and a pixeltransfer pulse output circuit (FIG. 28B) having a same configuration asthe pixel reset pulse output circuit. The configuration of the actualmultiplexer has a number of rows in the pixel portion of suchconfigurations. M11 and M21 are transistors for fetching the output ofthe vertical scanning circuit 202, M12 and M22 are transistors forfetching the output of the electronic shutter scanning circuit 203, M13and M23 are transistors for setting simultaneous reset, M14 is a readingreset pulse output transistor, M15 is an electronic shutter reset pulseoutput transistor, M24 is a reading transfer pulse output transistor,M25 is an electronic shutter transfer pulse output transistor, and C1 toC12, and C21 to C22 are capacitances. Further, RST is a reading resetpulse, ERST is an electronic shutter reset pulse, TR is a readingtransfer pulse, ETR is an electronic shutter transfer pulse, VDRRS is ascanning circuit output fetching pulse, ARST is a simultaneous resetpulse, MPXDD is a simultaneous reset power supply, φV is a reading rowselecting line, φVE is an electronic shutter row selecting line, φRST isa pixel reset pulse line, φTR is a pixel transfer pulse line.

Here, suppose that the simultaneous reset pulse line ARST and thesimultaneous reset power supply MPXDD are connected to all the rows ofthe multiplexer 204. Further, the simultaneous reset pulse line ARST,the simultaneous reset power supply MPXDD, and the simultaneous resetsetting SW transistor M13 which are connected to the φVE side areportions added for realizing the simultaneous reset action, and operateindependently of the scanning circuit.

In the embodiment, because the transistors used for configuring therespective pixel cells and the multiplexer 204 is configured of only onetype transistors (N channel MOS transistors), the number ofmanufacturing processes can be reduced.

Hereinafter, the reset action and the reading operation for the pixelcells of FIG. 27 will be described. First, the reset action for thepixel cells will be described. The power supply line for the pixel cellsVDDCEL (208 in FIG. 26) is set to the “H” level. Next, when the LGCEL(210 in FIG. 26) is set to the “H” level, an electric current issupplied to the respective pixel cells PIX211 to PIX233, and the MOStype solid-state imager apparatus is made to be in an operating mode.When the M2 is turned on by the φRST, the FD unit 220 is set to the “H”level which is the same as the VDDCEL. Next, after the M2 is turned offby the φRST, when the M1 is turned on by the φTR, electric chargeaccumulated in the PD1 is transferred to the FD unit 220 via the M1. Inaccordance therewith, the electric charge in the PD1 is cleared, and areset action is carried out. Thereafter, the M1 is turned off by theφTR, and the PD1 is made to be in a state of accumulating electriccharge, and the reset action is completed.

Further, after the VDDCEL is set to the “L” level, when the resettransistor M2 is turned on by the φRST, the FD unit 220 is set to the“L” level which is the same as the VDDCEL. Next, the FD unit 220maintains to be at the “L” level due to the M2 being turned off by theφRST, and in accordance therewith, the pixel cells are made to be in astate of non-operating. A light which is incident in this state isaccumulated as electric information in the PD1.

Next, reading operation for the pixel cells will be described. First,the VDDCEL is set to the “H” level. Next, the FD unit 220 is set to the“H” level which is the same as the VDDCEL due to the M2 being turned onby the φRST. Next, after the M2 is turned off by the φRST, the M1 isturned on by the φTR, and the electric charge accumulated in the PD1 istransferred to the FD unit 220. Thereafter, the M1 is turned off by theφTR, and the transmission is completed.

The electric charge in the FD unit 220 is outputted as a voltage to theoutput line for the pixels PIXOUT via the M3. Next, the VDDCEL is set tothe “L” level, the M2 is turned on by the φRST, and the PD unit 220 isset to the “L” level which is the same as the VDDCEL. Thereafter, the FDunit 220 is made to be maintained to be at the “L” level due to the M2being turned off by the φRST. At this point in time, the reading of thesignals from the pixels is completed.

The operations of the multiplexer 204 of FIGS. 28A and 28B will bedescribed. As described above, both of FIGS. 28A and 28B have the sameconfigurations, and because the operations thereof are substantiallysame, only the operation of the pixel reset pulse output circuit of FIG.28A will be described here.

When a level of the φV inputted in a state in which the RST is made tobe at the “L” level is at, for example, the “H” level, when the M11 isturned on by the VDRRS, signals at the “H” level of the φV areaccumulated in the capacitance C11. At that time, because the M14 isturned on, the reading reset pulse RST is outputted as is to the φRST.In the same way even after the M11 is turned off by the VDRRS, the RSTis outputted to the φRST. Here, when the RST is at the “H” level, the“H” level is inputted to the φRST of the pixel cell on a specific row,and the reset action for the pixel cells described above is executedwith respect to the pixel cells on the specific row.

On the other hand, when the φV is at the “L” level, signals at the “L”level are accumulated in the capacitance C11. In this case, because theM14 is being turned off, the RST is not outputted to the φRST even ifthe RST is at any signal level.

Although the φV was described, the description of the φVE is in the sameway. In this way, only when the φV and the φVE are at the “H” level, theRST or the ERST is outputted to the φRST.

Further, when the ARST is set to the “H” level in a state in which theERST is made to be at the “L” level, the M13 is turned on, signals atthe “H” level of the MPXDD are stored in the C12s on all the rows. Atthis time, the M15 is turned on, and the ERST is outputted as is to theφRST. Even after the M13 is turned off by the ARST, the ERST isoutputted to the φERST in the same way. Here, when the ERST is at the“H” level, the “H” level is inputted to the φRSTs of the pixel cells onall the rows, and the reset action for the pixel cells described aboveis carried out with respect to all the pixels simultaneously.

In the present embodiment, there is provided the feature that the resetaction in units of rows described above and the all the pixelssimultaneous reset action are executed while being switched byselectively driving the ARST and the VDRRS (for example, the all thepixels simultaneous reset action is carried out in a case ofphotographing a still image, and the reset action in units of rows iscarried out in a case of photographing a moving picture.

Hereinafter, such two types of reset actions will be described in detailwith reference to the timing charts of FIGS. 29 to 31.

FIG. 29 is the timing chart for explanation of the reset action in unitsof rows, and shows signal waveforms appearing in the respective signallines. In FIG. 29, there are shown the waveforms of the VDDCEL (powersupply line for pixel cells), the LGCEL (load pulse line for pixelcells), the RST (reading reset pulse line), the TR (reading transferpulse line), the ERST (electronic shutter reset pulse line), the ETR(electronic shutter transfer pulse line), the VDRRS (pulse line forfetching the outputs of the vertical scanning circuit), the ARST(simultaneous reset pulse line), the φV1, the φV2, and the φV3 (readingrow selecting lines), the φVE1, the φVE2, and the φVE3 (electronicshutter selecting lines), the φRST1, the φRST2, and the φRST3 (pixelreset pulse lines for each row), the φTR1, the φTR2, and the φTR3 (pixeltransfer pulse lines for each row), and a mechanical shutter output.

As shown by the φRST1, the φRST2, the φRST3, and the φTR1, the φTR2, theφTR3, reading and reset for the signals from the pixel cells are carriedout in timings different in each row. In this case, exposure times inthe respective rows are determined so as to be the same. However, theexposure starting timings are different from each other.

Then, in order to make the exposure starting timings coincide with oneanother, it has been carried out that, after the reset actions in allthe rows are completed, an exposure timing is determined so as to besynchronous with a open/close timing of a mechanical shutter (here, afocal-plane shutter or a lens shutter). FIG. 30 shows the operation atthat time.

However, in a method in which exposures with respect to the pixel cellsin the respective rows are carried out in a same timing by using thereset action in units of rows and the mechanical shutter together,because the exposures are carried out after the reset actions withrespect to all the pixel cells, there is the problem of a delay in atime from a start of the reset action to the time when the mechanicalshutter is fully opened, in particular, in a case of fetching a stillimage. Then, here, by using the simultaneous reset action for all thepixel cells, in a case of photographing a still image, all pixel cellsimultaneous reset is carried out.

FIG. 31 is a timing chart for explanation of a driving timing accordingto the embodiment for which a simultaneous reset is used, and the resetaction is carried out onto all pixel cells simultaneously, and anoperation of reading signals from the pixels is carried out in units ofrows as shown in FIG. 29. Because the names of the respective lines areas those described in FIG. 29, descriptions thereof will be omittedhere.

First, in a state in which the ERST and the ETR are made to be at the“L” level, the M113 and the M23 are turned on with respect to all therows due to the ARST being made to be at the “H” level, and signals atthe “H” level are accumulated in the C12 and C22. In accordancetherewith, the M15 and the M25 are already in an ON-state. Next, theARST is made to return to be at the “L” level, and the M13 and the M23are turned off. Thereafter, after the VDDCEL or a bias supply is set tothe “H” level, the ERST is made to be at the “H” level. This ERST isoutputted to the φRST via the M15 which has been in an ON-state, and theφRSTs of the pixel cells on all the rows are set to the “H” level. Inaccordance therewith, the M2 is turned on, and the FD units 220 of allthe pixel cells are raised to the VDDCEL level (here, the “H” level).

Thereafter, the ERST is made to return to the “L” level, and the φRSTsof the pixel cells on all the rows are made to be at the “L” level, anddue to the M2 being turned off, the FD units 220 of all the pixel cellsare maintained to be at the “H” level. Continuously, due to the ETRbeing made to be at the “H” level, the φTRs of the pixel cells on allthe rows are set to the “H” level. In this state, the electric chargeaccumulated in the PD1 is transferred to the FD units 220 via the M1,and due to the electric charge in the PD1 being cleared, simultaneousreset action for all the pixel cells is carried out.

Thereafter, due to the ETR pulse being made to return to the “L” level,the φTRs of the pixel cells on all the rows are made to be at the “L”level, and the M1 is turned off, and the PD1 is made to be in a state ofaccumulating electric charge, and the simultaneous reset action iscompleted.

Next, after the VDDCEL or the bias supply is set to the “L” level, theERST is made to be at the “H” level from the electronic shutter scanningcircuit 203. This ERST is outputted to the φRST via the M15 which hasbeen in an ON-state, and the φRSTs of the pixel cells on all the rowsare set to the “H” level. In accordance therewith, the M2 is turned on,and the FD units 220 are made to be at the “L” level. Next, due to theERST being made to return to the “L” level, the φRSTs of the pixel cellson all the rows are made to be at the “L” level, the M2 is turned off,the FD units 220 are maintained to be at the “L” level, and all thepixel cells are made to be in a stand-by state.

The exposure terminations of all the pixel cells are in a same timing byclosing the mechanical shutter. Thereafter, the routine proceeds to areading operation from the pixel cells. However, in this case, thereading operation is carried out for each row. First, in the first row,the M11 and the M21 are turned on by the VDRRS, and the output φV1 ofthe vertical scanning circuit 202 is fetched into the C11 and the C21 ofthe multiplexer 204. In this case, the φV2 and the φV3 are not driven.Accordingly, because the “H” level of the RST is outputted to the φRST1in the first row and the M2 is turned on, only the FD units 220 of thepixel cells in the first row are raised to the VDDCEL. Thereafter, afterthe RST is made to return to the “L” level, the TR is set to the “H”level, and this is outputted to the φTR and the M1 is turned on, so thatthe electric charge in the PD1 in the first row is transferred to thePD220 via the M1. Thereafter, when the TR is made to return to the “L”level, the transferred electric charge is outputted as a voltage to thePIXOUT as the pixel signal. The pixel signal is transferred to the noisesuppressing circuit 205 via the V1 to the V3. Thereafter, the VDDCEL isset to the “L” level, and due to the RST being made to return to the “L”level after the “H” level is set to the RST, the FD units 220 aremaintained to be at the “L” level, and the pixel cells in the first roware made to be in a stand-by state. The output from the noisesuppressing circuit 205 is read out to the sensor output line OUT viathe horizontal scanning circuit 206 and the output amplifier 207.

After the pixel signals in the first row of the pixel portion 201 areread in this way, next, the pixel signals in the second row of the pixelportion 201 are read.

However, at this time, the same operation is repeated in response to thesignal of the φV2, and the pixel signals of the pixel cells in thesecond row are read. With respect to the third row, the pixel signals ofthe pixel cells in the third row are read in response to the signal ofthe φV3.

FIG. 32 is a diagram showing a configuration of a MOS type solid-stateimager apparatus according to a modified example of the presentinvention. FIGS. 33A and 33B are diagrams showing configurations of themultiplexer 204 corresponding to the configuration of FIG. 32. In thismodified example, it is configured such that some of the multiplexershown in FIG. 28A and FIG. 28B are changed. However, the basicoperations are the same as those of the multiplexer in FIG. 28A and FIG.28B. Concretely, a drain of the M13 (and the M23) is connected to, notthe MPXDD, but the ARST. In accordance therewith, the MPXDD can befallen into disuse. In the M13 (and the M23) having such aconfiguration, electrical continuity only in one-way is possible, andthe signal of the ARST can be transferred to the C12 (and the C22) onlywhen the ARST is at the “H” level. When the ARST is at the “L” level,the M13 (and the M23) is made to be in an open-state

In accordance with the present invention, because the reset action inunits of rows and the simultaneous reset action are executed whileappropriately switching those, a delay at the time of fetching an imagecan be reduced.

Further, in accordance with the present invention, the simultaneousreset action can be executed by adding a simple circuit configuration.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A solid-state imager apparatus comprising a solid-state imager havingcolor filters in a predetermined arrangement, the solid-state imagerapparatus having a mode in which all pixels are progressively outputted,and a mode in which interlace reading for pixels is carried out in oneframe and pixel signals of pixels which are at a same color phase amongcolor phase coding regulated by the color filters are averaged withrespect to the pixels and outputted.
 2. A solid-state imager apparatusaccording to claim 1, wherein the averaging is carried out only in ahorizontal direction, and is not carried out in a vertical direction. 3.A solid-state imager apparatus according to claim 1, wherein switchingof the mode in which all pixels are progressively outputted and the modein which pixels are averaged and outputted is carried out by driving andcontrolling the horizontal and vertical scanning circuits and the signalaveraging switch unit.
 4. An XY address type solid-state imagerapparatus comprising a solid-state imager in which a plurality of pixelshaving color filters in which at least some of those are Bayer-patternedare two-dimensionally arranged, and horizontal and vertical scanningcircuits to read the pixels, the solid-state imager apparatuscomprising: a signal averaging switch unit which averages pixel signalsof pixels which are at a same color phase among color phase codingregulated by the color filters; and a mode in which all pixels areprogressively outputted on the basis of controls of the scanningcircuits, and a mode in which interlace reading for pixels is carriedout in one frame, and signals which have been averaged by the signalaveraging switch unit with respect to the pixels are outputted.
 5. Asolid-state imager apparatus according to claim 4, wherein pixels of apart of the solid-state imager are shading pixels, and the signalaveraging switch unit further averages signals of predetermined pixelsamong signals relating to the shading pixels.
 6. A solid-state imagerapparatus according to claim 5, wherein reading is progressively carriedout in one frame with respect to the shading pixels.
 7. A solid-stateimager apparatus according to claim 5, wherein the signal averagingswitch unit comprises a shading pixel signal averaging switch unit andan effective pixel signal averaging switch unit, and controls whether ornot it is possible to average the signals relating to the shading pixelsdue to the shading pixel signal averaging switch unit by a first signal,and controls whether or not it is possible to average the pixel signalsof the pixels which are at a same color phase among color phase codingregulated by the color filters due to the effective pixel signalaveraging switch unit by a second signal.